One type of prior non-volatile semiconductor memory device is a flash electrically erasable and electrically programmable read-only memory ("EEPROM"). The flash EEPROM includes a memory array of field-effect memory cells. By flash, it is meant that the memory array may be erased in its entirety or section by section. A field-effect memory cell typically includes a source, a drain, a floating gate, and a control gate. The cell is typically a programmed cell or an erased cell. The programmed cell has a floating gate that is typically charged with electrons. The erased cell has a floating gate that typically has relatively fewer electrons compared to a programmed cell. A reprogramming sequence may include the following steps: 1) programming the cells by accumulating electrons within their floating gates regardless of whether or not each cell has been previously programmed, 2) erasing the cells by removing the electrons from their floating gates, and 3) selectively programming the memory array. After reprogramming, each erased cell should have a drain current greater than about 10 .mu.A, and each programmed cell should have a drain current less than about 0.2 nA when the control gate of each cell is biased at about the power supply voltage and the drain of each cell is biased at about 1.0 V.
Within this application, a cell typically has two types of threshold voltages. The floating gate threshold voltage (VTFG) is the floating gate potential that gives a drain current of about 10 .mu.A when the source is grounded and the drain is at a potential of about 1 V. One may choose a different drain current limit or drain potential for determining VTFG. The floating gate potential cannot be directly measured because the floating gate is electrically floating. The control gate typically induces a potential increase on the floating gate due to capacitive coupling. The control gate threshold voltage (VTCG) is the control gate potential that gives a drain current of about 10 .mu.A when the source is grounded and the drain is at a potential of about 1 V. One may choose a different drain current limit or drain potential for determining VTCG. VTCG is typically higher than VTFG because the control gate coupling ratio typically is less than one.
FIG. 1 is a graph illustrating a typical VTCG distribution of memory cells in a memory array after the cells are erased. The x-axis is VTCG, and the y-axis is the cumulative fraction of cells having a VTCG equal to or lower than a given voltage. After erasing, many cells have a VTCG below 1.0 V and are called "tail cells" within this patent application. The number of tail cells is generally determined by the shape of the VTCG distribution curve. A tail cell may have a VTCG less than 0.0 V. Within the tail cell distribution, some of the tail cells are referred to as "over-erased cells" because their VTCG is below a predetermined potential, such as about 0.5 V, for example. One may set a different VTCG limit to determine whether or not a cell is an over-erased cell.
Problems may occur when an over-erased cell is present including a programming and read sensing problems and slower read access time. The problems are best described using specific examples. In the examples below, a flash EEPROM has a memory array including Cell 1 and Cell 2. The drains of both cells are electrically connected to a bit line, and the sources for both cells are grounded. Cell 1 has a VTFG after erase of 1.2 V, and Cell 2 is an over-erased cell having a VTFG after erase of 0.2 V. Both cells have a drain coupling ratio of 0.1 and a control gate coupling ratio of 0.5.
The memory array is to be reprogrammed so that Cell 1 becomes a programmed cell and Cell 2 becomes an erased cell. Both cells are programmed and erased. After the erase step, the memory array is selectively programmed. Cell 1 is programmed by taking Cell 1's control gate to a potential of about 12 V, and the bit line to a potential of about 6 V. Because of drain coupling and control gate coupling, the floating gate potential is about 6.6 V during selective programming. During selective programming, current typically flow through Cell 1 because the floating gate potential (about 6.6 V) is greater than its VTFG (1.2 V), and Cell 1 should program in about 10 .mu.s. However, Cell 1 is influenced by over-erased Cell 2. Cell 2's source and Cell 2's control gate are typically grounded because Cell 2 is not being programmed. Cell 2's drain is at a potential of about 6 V due to the bit line. The floating gate of Cell 2 has a potential of about 0.6 V because of the drain coupling. Therefore, Cell 2 also has a significant drain current during programming because its VTFG (0.2 V) is less than its floating gate potential (0.6 V). This extra current reduces the bit line voltage slowing the selective programming of Cell 1.
The program sensing circuit typically cannot determine whether a bit line has a cell that is difficult to program or if the bit line has an over-erased cell. The selective programming continues until a program sensing circuit determines that Cell 1 is successfully programmed, continues for a predetermined number of cycles, such as 25 cycles of about 10 .mu.S each, or continues for a predetermined amount of time, such as approximately 250 .mu.S. If Cell 1 fails to program within the specified number of pulses or time, then the device is considered as failing programming.
Even if Cell 1 is reprogrammed, a problem may occur when Cell 1 is read. When a cell is read, its control gate typically is at about the power supply potential and its bit line typically is at a potential of about 1 V. A programmed cell should have a drain current less than about 0.2 nA, and an erased cell should have a drain current greater than about 10 .mu.A. Even if Cell 1 is programmed (as determined by the program sensing circuit), the bit line may have a current between about 0.2 nA and about 10 .mu.A because Cell 2 (an over-erased cell) is on the same bit line during reading. The read sensing circuit, which is different from the program sensing circuit, may incorrectly determine that Cell 1 is an erased cell. If the read sensing circuit incorrectly determines that a cell is erased when it is programmed, the device is non-functional.
Even if Cell 1 can be read, the read access time may be longer. If the drain current of Cell 1 is higher than about 0.2 nA, the read sensing circuit may need a longer time to determine whether the cell is programmed or erased. The read access time may be about 90 ns instead of about 80 ns. Slower read access times are not desired.